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(Invited) 4H-SiC Ion Implanted Bipolar Junctions: Relevance of the 1950°C Temperature for Post Implantation Annealing
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Ion implantation is a relevant technology for the fabrication of p-n interfaces in several SiC electronic devices; ion implanted source/drain and body regions in commercial 4H-SiC MOSFET [1] and buried grids in JBSD [2] can be cited as examples. Previous studies have shown that the efficiency of the electrical doping by ion implantation increases with the increase of the post implantation annealing temperature [3-4] and time [5]. Previous studies have also shown that n-type 4H-SiC epi-layers treated at so high temperatures as those used for the post implantation annealing of 4H-SiC, contain Z1/Z2 defect concentrations of increasing values with the increase of the processing temperature [6-7]. Z1/Z2 is a lifetime killer defect is 4H-SiC [8]; it is always present at the same time that the EH7 defect. Z1/Z2 and EH7 are univocally associated to the double acceptor state at 0.7 eV from the conduction band (CB) and the single donor one at 1.55 eV from CB, respectively, of the structural defect carbon vacancy Vc in 4H-SiC [9].
This presentation will highlight two recent results obtained by the use of the 1950°C temperature for the post implantation annealing of Al+ ion implanted 4H-SiC. One result concerns the hole transport in very heavy doped 4H-SiC(Al) layers. The other result concerns the defects that may account for the area component of the forward characteristic of vertical 4H-SiC p-i-n diodes with Al+implanted anodes.
The very efficient electrical activation process at 1950°C and an Al implanted concentration above the Al solubility limit of 2x1020 cm-3 in 4H-SiC [10] allow us to obtain p-type 4H-SiC(Al) materials with a conductivity temperature dependence that is consistent with an hole transport through impurity band states and in particular through a variable range hopping mechanism at temperatures that ranges from below till around room temperature, depending on the value of the implanted Al concentration. Positive and negative drawback for application of these doping conditions in practical SiC devices will be discussed.
4H-SiC p-i-n vertical diodes with Al+ implanted anodes and different perimeter to area ratios have been used to obtain the area and perimeter component of the forward and reverse current-voltage (I-V) curves of a batch of diodes obtained with a post implantation annealing temperature of 1950°C [11]. It is worthwhile to remark that the specific area and perimeter curves are typical of processing and of 4H-SiC material parameters, i.e. they are independent of the device geometry [12-13]. Thermal activation energies of 1.65 eV, 0.5 eV and 0.2 eV have been obtained for the defects responsible of generation and recombination currents of this diodes batch. These energy values may be the labels of different types of defects in 4H-SiC, both impurities and intrinsic defect (Vc in particular). These hypotheses have been used in the Synopsys Sentaurus TCAD suite [14] for fitting the forward area current density of the studied diodes. Fig. 1 shows an example of the simulation outputs in the case of traps associated to the three level obtained from the diode I-V curves. Electron and hole carrier life-times are the fitting parameters of this study. Other point defects will be considered and the life-time values for reproducing experimental data will be discussed with respect to the processing parameters used during diode fabrication.
[1] last accessed on April 7, 2016: http://www.wolfspeed.com/power/products/sic-mosfets
[2] J.-K. Lim, D. Peftitsis, D.-P. Sadik, et al., Mater. Sci. Forum 778-780 (2014) 804-807.
[3] R. Nipoti, R. Scaburri, A. Hallén, et al., J. Mater. Res. 28 (2013) 1-6.
[4] R. Nipoti, A. Nath, S.B. Quadri, et al., J. Electron. Mater. 41 (2012) 457-465.
[5] R. Nipoti, A. Parisini, S. Vantaggio, et al. Mater. Sci. Forum 858 (2016) 523-526.
[6] H. M. Ayedh, V. Bobal, R. Nipoti, et al., J. Appl. Phys. 115, 012005 (2014).
[7] H. M. Ayedh, A. Hallén, and B. G. Svensson, J. Appl. Phys. 118, 175701 (2015).
[8] P. B. Klein, B. V. Shanabrook, S. W. Huh, A. Y. Polyakov, et al., Appl. Phys. Lett. 88, 052110 (2006).
[9] N. T. Son, X. T. Trinh, L. S. Løvlie, B. G. Svensson, et al., Pys. Rev. Lett. 109, 187603 (2012).
[10] M. K. Linnarsson, U. Zimmermann, et al., Appl. Surf. Science 203-204 427 (2003).
[11] M. Puzzanghera and R. Nipoti, Mater. Sci. Forum 858 (2016) 773-777.
[12] U. Grossner, F. Moscatelli, and R. Nipoti, Mater. Sci. Forum 778-780 (2014) 657-660.
[13] A. Nath, Mulpuri V. Rao, et al., IEEE proceedings "Ion Implantation Technology (IIT), 2014 20th International Conference on", Portland, OR, USA, pp. 1-4.
[14] last accessed on March 23, 2016: http://www.synopsys.com/Tools/TCAD
Figure 1
The Electrochemical Society
Title: (Invited) 4H-SiC Ion Implanted Bipolar Junctions: Relevance of the 1950°C Temperature for Post Implantation Annealing
Description:
Ion implantation is a relevant technology for the fabrication of p-n interfaces in several SiC electronic devices; ion implanted source/drain and body regions in commercial 4H-SiC MOSFET [1] and buried grids in JBSD [2] can be cited as examples.
Previous studies have shown that the efficiency of the electrical doping by ion implantation increases with the increase of the post implantation annealing temperature [3-4] and time [5].
Previous studies have also shown that n-type 4H-SiC epi-layers treated at so high temperatures as those used for the post implantation annealing of 4H-SiC, contain Z1/Z2 defect concentrations of increasing values with the increase of the processing temperature [6-7].
Z1/Z2 is a lifetime killer defect is 4H-SiC [8]; it is always present at the same time that the EH7 defect.
Z1/Z2 and EH7 are univocally associated to the double acceptor state at 0.
7 eV from the conduction band (CB) and the single donor one at 1.
55 eV from CB, respectively, of the structural defect carbon vacancy Vc in 4H-SiC [9].
This presentation will highlight two recent results obtained by the use of the 1950°C temperature for the post implantation annealing of Al+ ion implanted 4H-SiC.
One result concerns the hole transport in very heavy doped 4H-SiC(Al) layers.
The other result concerns the defects that may account for the area component of the forward characteristic of vertical 4H-SiC p-i-n diodes with Al+implanted anodes.
The very efficient electrical activation process at 1950°C and an Al implanted concentration above the Al solubility limit of 2x1020 cm-3 in 4H-SiC [10] allow us to obtain p-type 4H-SiC(Al) materials with a conductivity temperature dependence that is consistent with an hole transport through impurity band states and in particular through a variable range hopping mechanism at temperatures that ranges from below till around room temperature, depending on the value of the implanted Al concentration.
Positive and negative drawback for application of these doping conditions in practical SiC devices will be discussed.
4H-SiC p-i-n vertical diodes with Al+ implanted anodes and different perimeter to area ratios have been used to obtain the area and perimeter component of the forward and reverse current-voltage (I-V) curves of a batch of diodes obtained with a post implantation annealing temperature of 1950°C [11].
It is worthwhile to remark that the specific area and perimeter curves are typical of processing and of 4H-SiC material parameters, i.
e.
they are independent of the device geometry [12-13].
Thermal activation energies of 1.
65 eV, 0.
5 eV and 0.
2 eV have been obtained for the defects responsible of generation and recombination currents of this diodes batch.
These energy values may be the labels of different types of defects in 4H-SiC, both impurities and intrinsic defect (Vc in particular).
These hypotheses have been used in the Synopsys Sentaurus TCAD suite [14] for fitting the forward area current density of the studied diodes.
Fig.
1 shows an example of the simulation outputs in the case of traps associated to the three level obtained from the diode I-V curves.
Electron and hole carrier life-times are the fitting parameters of this study.
Other point defects will be considered and the life-time values for reproducing experimental data will be discussed with respect to the processing parameters used during diode fabrication.
[1] last accessed on April 7, 2016: http://www.
wolfspeed.
com/power/products/sic-mosfets
[2] J.
-K.
Lim, D.
Peftitsis, D.
-P.
Sadik, et al.
, Mater.
Sci.
Forum 778-780 (2014) 804-807.
[3] R.
Nipoti, R.
Scaburri, A.
Hallén, et al.
, J.
Mater.
Res.
28 (2013) 1-6.
[4] R.
Nipoti, A.
Nath, S.
B.
Quadri, et al.
, J.
Electron.
Mater.
41 (2012) 457-465.
[5] R.
Nipoti, A.
Parisini, S.
Vantaggio, et al.
Mater.
Sci.
Forum 858 (2016) 523-526.
[6] H.
M.
Ayedh, V.
Bobal, R.
Nipoti, et al.
, J.
Appl.
Phys.
115, 012005 (2014).
[7] H.
M.
Ayedh, A.
Hallén, and B.
G.
Svensson, J.
Appl.
Phys.
118, 175701 (2015).
[8] P.
B.
Klein, B.
V.
Shanabrook, S.
W.
Huh, A.
Y.
Polyakov, et al.
, Appl.
Phys.
Lett.
88, 052110 (2006).
[9] N.
T.
Son, X.
T.
Trinh, L.
S.
Løvlie, B.
G.
Svensson, et al.
, Pys.
Rev.
Lett.
109, 187603 (2012).
[10] M.
K.
Linnarsson, U.
Zimmermann, et al.
, Appl.
Surf.
Science 203-204 427 (2003).
[11] M.
Puzzanghera and R.
Nipoti, Mater.
Sci.
Forum 858 (2016) 773-777.
[12] U.
Grossner, F.
Moscatelli, and R.
Nipoti, Mater.
Sci.
Forum 778-780 (2014) 657-660.
[13] A.
Nath, Mulpuri V.
Rao, et al.
, IEEE proceedings "Ion Implantation Technology (IIT), 2014 20th International Conference on", Portland, OR, USA, pp.
1-4.
[14] last accessed on March 23, 2016: http://www.
synopsys.
com/Tools/TCAD
Figure 1.
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