A Power-Efficient and Noise-Resilient Domino Logic Architecture with Adaptive Keeper Control for Wide Fan-In Applications

Abstract In this paper, a power efficient and noise resilient domino logic architecture is proposed for wide fan-in dynamic circuits. Conventional domino logic suffers from high power dissipation, leakage current and reduced robustness due to keeper contention and charge sharing in large PDN. To mitigate these limitations an adaptive keeper regulation scheme is introduced to suppress unnecessary contention during evaluation while preserving dynamic node stability. In addition, the PDN is restructured using a stacked footer transistor with parallel discharge path to mitigate subthreshold leakage and alleviate charge sharing without degrading evaluation speed. The proposed DLG is designed and simulated using 90 nm CMOS technology in Cadence Virtuoso. Simulation results demonstrate 54% improvements in noise margin, 34% reductions in power consumption and 33% reductions in PDP and EDP, along with improved tolerance to process variations compared to 32-in conventional domino logic gate. Furthermore, a 128-bit wide fan-in multiplexer is implemented to validate the effectiveness of proposed approach.