Low Area/Energy Consumption Overhead and Robust Logic Locking Designs for Hardware Obfuscation Exploring Negative Capacitance FETs with Circuit Co-Design Techniques

Logic locking has been established as a promising hardware obfuscation technique used in modern integrated circuits (ICs) to protect intellectual property (IP) from various hardware attacks. CMOS based logic locking design techniques introduce high propagation delay and energy consumption overhead with CMOS scaling due the extra logic gates introduced (increased area) for logic locking. In this work, Negative capacitance FETs (NCFETs) with circuit co-design has been explored for the first time to demonstrate robust and low area/energy consumption overhead logic locking designs for hardware obfuscation applied to a PRIDE S-box design at V DD =0.5V. At circuit level, we have explored the suitability of static complementary logic (SCL) vs pass transistor logic (PTL) with NCFETs for effective logic locking designs. Pass transistor logic designs though seem to be area efficient but are not robust with CMOS technology and this has been overcome using NCFETs with an optimal t fe value to get full logic swing for robust designs. Due to the steep slope characteristics of NCFETs, NCFET based PRIDE S-box logic locking design with SCL exhibit ~30.10% energy consumption overhead when compared to the NCFET SCL design without logic locking, whereas baseline static CMOS design with logic locking incur ~37.56% energy consumption overhead. Further, NCFET PTL based PRIDE S-box with logic locking design at an optimal t fe reduce the energy consumption by ~61.62% and number of transistors (area) by ~ 48% when compared to the equivalent NCFET design with logic locking using SCL.